The present invention relates to a method for fabricating a thin capacitor dielectric layer over a layer of polysilicon.
One of the key process issues for realizing high performance analog and digital CMOS circuits is the ability to fabricate precision, high value, poly to poly capacitors, at the same time as low resistance poly gates and interconnect.
A common technique for producing precision poly to poly capacitors is to lightly dope the first level of poly (bottom plate) to 100 ohms /sq, so a very uniform dielectric can be grown at the same time the gate oxide is regrown. Second level poly is then used as the top plate.
Incorporating such a technique into a CMOS flow means that the sheet resistance of uncovered first level poly inside the tank is increased to around 200 ohms per square, due to the counterdoping action of the P+source/drain implant. (This could be avoided by including extra mask steps or merging levels). Outside the tank, the first poly sheet resistance is reduced by the N+source/drain implant to 40 ohms per square. For these reasons many process flows have used 1st poly primarily for the bottom plate of capacitors and low or natural V.sub.T N-channel transistors. 2nd poly, doped to around 15 ohms per square, can be used for regular gates, interconnect and capacitor top plates. High impedance poly resistors in such a process flow would require an extra mask step.
As the process is scaled, this type of flow becomes more important since a polycide layer for low sheet resistance gates and interconnect is required. This follows since the polycide sheet resistance increases with the number of heat treatment cycles and thermal oxidations that follow its deposition.
The main limitation of this technique is that the capacitor's dielectric thickness, and hence maximum value, is controlled by the regrown gate oxide thickness, used for regular gates (2nd poly). For a 700 A gate oxide process this limits the dielectric to about 1100 A (oxide grows faster on doped poly), resulting in a capacitance of 0.2 pF/mil.sup.2. Scaling the process to 3 microns and the gate oxide to 550 A does significantly increase the maximum capacitance achievable. For some analog integrated circuits the low value of capacitance/unit area means that the area occupied by capacitors is comparable to, or greater than, the rest of the circuitry! Any increase in capacitance will be useful in terms of reduced noise, improved power supply rejection and reduced area. These considerations become more important as the technology is scaled.
The present invention provides a demonstrated technique for fabricating poly to poly capacitors with a much higher capacitance/unit area, 0.8 pF/mil.sup.2. The technique utilizes a composite oxide/nitride/oxide dielectric whose thickness can be controlled independently of the regrown gate oxide process, without the requirement of an extra mask. The composite dielectric has very good integrity: typical breakdown for a 350 A composite layer is 24-30 V. Leakage measurements indicate characteristics similar to poly capacitors with an 800 A thermally grown oxide. In some of the test experiments the oxide and nitride layers were formed by LPCVD. These have exhibited high uniformity, better than 0.005%/mil or 3% across a 3" slice. A further advantage of using an LPCVD dielectric is that poly 1 can be doped to about 15 ohms per square since it is no longer necessary to thermally grow a uniform oxide. This gives the designer the flexibility of using both heavily doped 1st poly and silicided 2nd poly for interconnect.
A general problem in the development of analog and data conversion integrated circuits is the large area which is frequently required for capacitors. In many applications, it may be found that half of the integrated circuits area is taken up with capacitors. This means that the density of capacitors is the limiting factor in achieving further integration of such analog integrated circuits. If a capacitor could be reliably fabricated within the stream of MOS processing with higher specific capacitance, i.e. higher capacitance per unit area, then smaller capacitors could be used, and capacitors would not be such a burden on the density of analog integrated circuits.
Thus it is an object of the present invention of to provide a method for fabricating capacitors having high specific capacitance for analog and data conversion integrated circuits.
It is a further object of the present invention to provide a method for fabricating capacitors having high specific capacitance in a standard MOS process.
A further important limitation in many analog and telecommunications circuits is that the value of the capacitors must be precise, i.e. the specific capacitance of the as-fabricated capacitors should be constant, from lot to lot, to, e.g., three percent.
Thus it is an object of the present invention to provide a method for reproducibly fabricating capacitors having a desired predetermined specific capacitance.
Capacitors in many analog integrated circuit layouts are preferably fabricated between the first and second poly levels, usually over field oxide, to achieve greater integration. Moreover, it is often greatly preferable to form poly-to-poly capacitors rather than poly-to-silicon substrate capacitors, because a buried N+ or a depletion type implant is required to make contact to the lower plate of the capacitor. Otherwise, the lower plate of the capacitor will in effect be the whole substrate, i.e. one side of the capacitor is grounded. Secondly, if a depletion implant is used, so that the carrier concentration at the lower (substrate) plate of the capacitor is not extremely high, the depletion width will be modulated by the voltage on the capacitor top plate, i.e. the capacitor becomes a nonlinear element in which the capacitance is a variable function of voltage. If a heavy N+ doping is required under poly-to-substrate capacitors, this means that additional processing steps are required. However, forming a precision capacitor over a first poly level is particularly difficult, since the surface of the first poly level will never be as smooth as that of a monocrystalline polished semiconductor surface, that is, the surface of even good poly will normally have a certain amount of unevenness. This unevenness can significantly affect the thickness of an oxide which is formed over the poly. It not only leads to uncertainty in the average specific capacitance, but also can cause formation of areas where an oxide grown over poly is locally thin.
Thus it is a further object of the present invention to provide a method for reliable fabrication of uniform dielectrics over a polysilicon level. The roughness of the polysilicon surface means that pinholing through a dielectric grown over first poly can occur. This problem becomes particularly serious if the dielectric is a thin one, as is required for high specific capacitance. This is a major concern in large analog integrated circuits, since the large total area devoted to capacitors means that even a small density of capacitor pinholes can cause drastic yield degradation.
Thus it is a further object of the present invention to provide a thin poly-to-poly dielectric having a very low density of pinholes.
In double poly processes, a regrown gate oxide is normally used to form transistors having second poly gates. That is, after the first poly level has been completely formed, the areas where transistors and second poly are to be formed are cleared down to silicon, and the gate oxides for second poly transistors are grown from scratch. However, the oxidizing conditions which permit growth of the second gate oxide also promote growth of oxide over the first poly level. Moreover, oxide normally grows faster on doped poly than on crystalline silicon under the same conditions, so that a thicker oxide will be formed over the first poly level. Where the oxide has already been formed over the first poly level before growth of the second gate oxide, as is typical, the oxide thickness over the first poly will be increased by the oxidizing conditions.
The second gate oxide will of course normally be grown to a precisely controlled thickness, but the simultaneous thickness increase of the oxide over the first poly will be uncontrolled. The chief reason for this is because of doping uncertainty. The oxidizing rate is a function of the polysilicon doping level, and the doping level itself cannot be precisely controlled in highly conductive POCl.sub.3 -doped polysilicon. Even if the polysilicon doping is performed by ion implantation, the average doping level in polysilicon will still be sensitive to the thickness of the polysilicon level deposited, which is also normally not a parameter which can be precisely controlled.
Thus it is an object of the present invention to provide a method for growth of a second gate oxide without any uncontrolled change in the thickness of an existing oxide over a first polysilicon level.
Thus it is an object of the present invention to provide a method for growth of a second gate oxide without simultaneously growing a thick oxide over first poly.
It is a further object of the present invention to provide a method for growing a second gate oxide without increasing the thickness of a dielectric over a first poly level.
A further problem with formation of capacitors is uniformity of the specific capacitance across the wafer. This problem is most acute in data conversion circuits where nonuniformity of capacitors can sacrifice several bits of accuracy. If integrated data conversion circuits are to have performance competitive with custom-trimmed hybrid circuits, uniform specific capacitance is a must. This is also a problem with switched-capacitor filtering, where nonuniformity can substantially degrade filter characteristics.
Thus it is a further object of the present invention to provide a method for forming poly-to-poly capacitors with highly uniform specific capacitance across the wafer.
In the present invention a composite oxide/nitride/oxide dielectric is used over the first poly level, instead of the thermal oxide taught by the prior art. This means that very thin dielectrics can be used over first poly which have very high dielectric integrity (low level of pinholes) and very high dielectric strength (breakdown voltage). Moreover, the dielectrics formed by the present invention are virtually unaffected by the normal second gate oxide growth cycle, so that the problem of uncontrolled thickness increase vanishes.
The problems described above are exacerbated in high voltage circuits, particularly in high voltage telecommunications circuits. Since the oxide thickness must be extremely high in these circuits anyway, to prevent gate/drain breakdown and excessive injection of hot carriers into the gate oxide, the problem of thickening of the oxide over the first poly during the growth of the second poly is exacerbated. That is, a typical thickness for the second gate oxide in a high voltage CMOS process would be 600 angstroms, and while 600 angstroms of oxide are grown on silicon typically 1000 angstroms will be grown on doped poly, or the thickness of an existing oxide layer on poly would be increased.
It is a further object of the present invention to provide a method for fabricating high voltage MOS integrated circuits, in which the thickness of the dielectric between the first and second poly levels can be selected to be equal to or less than the thickness of the second gate oxide.
According to the present invention, there is provided:
An integrated circuit structure comprising: PA0 a substrate; PA0 a first polysilicon layer overlying portions of said substrate; PA0 a dielectric layer on said first polysilicon layer; and PA0 a second polysilicon layer on said dielectric; PA0 providing a substrate; PA0 providing a first conductive layer over said substrate, said first conductive layer being polycrystalline and comprising silicon; PA0 forming a silicon dioxide layer over said first conductive layer; PA0 forming a silicon nitride layer over said silicon dioxide layer; PA0 clearing areas of said silicon substrate where a second plurality of transistors are to be formed; PA0 oxidizing said cleared areas of said silicon to form a plurality of second gate oxides, and simultaneously partially oxidizing said nitride layer, whereby a composite oxide/nitride/oxide dielectric is provided over said first conductive layer; and PA0 depositing a second conductive layer selectively over said locations of said second plurality of transistors and over portions of said first conductive layer.
wherein said dielectric comprises a silicon dioxide/silicon nitride/silicon dioxide composite.
According to the present invention there is provided:
A method for fabricating a dielectric over a first conductive layer in an integrated circuit fabrication, comprising the steps of: